The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 1998
Filed:
Jun. 05, 1997
Akira Miyoshi, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A partial product adder for summing up four partial products P0, P1, P2, and P3 which are binary numbers in twos-complement representation having different weights is composed of a carry save adder consisting of an array of 4:2 compressors each having four inputs. Of the four inputs of each 4:2 compressor, the input W presents the shortest propagation delay, while the inputs Y and Z compose critical paths. To implement sign extension of the first partial product P0 having the smallest weight, a logic circuit provides, in a plurality of digit positions higher than the sign digit P0s of the first partial product, values resulting from a logic operation between the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product having the second smallest weight. The first partial product P0 after sign extension is allocated to the input W of the carry save adder, while the plurality of upper digits of the input Z related to the second partial product P1 have their values fixed to 0. This reduces a time penalty accompanying the sign extension.