The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 1998
Filed:
Oct. 18, 1994
James Henry Hesson, Chittenden County, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A parallel multiply accumulator that provides a two's complement and unsigned multiply has a accumulator structure that minimizes the local and global interconnect lengths so that the design readily scales with advanced complementary metal oxide semiconductor (CMOS) integrated circuit (IC) technologies. The multiplier accumulator is formed with a plurality of identical panels, four in the preferred embodiment. Each identical panel implements the unique compensation necessary to form a multiplication/accumulation. The improved panel design is intended to operate in multiple panel designs and achieves a significant performance improvement. The improved multiply accumulator panel compensation is utilized for both two's complement compensation and according to the position of the panel within the overall array structure. Netlist generators are used to compile the netlist for both the main panel and the full adder arrays to sum the panels. This allows rapid generation of multiple arrays suitable for use in single and double precision arithmetic as well as extended precision arithmetic.