Method of fabricating a contact structure for a raised source/drain

Abstract

A method of fabricating a MOSFET device structure, wherein the MOSFET device structure includes field oxide regions, a layer of gate oxide formed on the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate, and LDD N- regions formed in the substrate adjacent the field oxide regions and beneath the sidewall spacers. A second layer of polysilicon is deposited over the above-described structure and a chemical mechanical polishing step is performed to self-align the polysilicon source/drain regions to the LDD N- substrate regions. N+ type dopant is then implanted into the gate poly and into the raised source/drain polysilicon regions. Next, a rapid thermal anneal step is performed to activate the N+ implant and to outdiffuse the N+ dopant from the polysilicon raised source/drain regions to form an N+ junction inside the N- LDD source/drain regions. A salicide oxide exclusion mask is then formed to protect the structure with the exception of the polysilicon raised source/drain regions and the polysilicon gate. An amorphization using heavy ion species is then performed to amorphize the surfaces of the gate/source/drain poly regions. A titanium film is then sputter deposited over the entire structure to form the first salicide phase in-situ. Unreacted titanium is then removed using a conventional wet etch and a dielectric layer is deposited and chemically mechanically polished to planarize the structure. The formation of the final titanium salicide phase is performed simultaneously with the densification of the dielectric layer.