Direct memory access channel architecture and method for reception of

Abstract

An ethernet receive channel, corresponding to an ethernet controller, is contained within a direct memory access (DMA) controller. The DMA controller is connected to the CPU bus of a computer system through a bus interface and is also connected to an I/O bus, which is coupled to one or more I/O controllers, including an ethernet controller. The ethernet receive channel contains a buffer and multiple register sets storing the number of packets to be received for a particular DMA transfer, the address where the next byte of the incoming ethernet packet will be written in memory, and control information for the transfer. The address registers are initially programmed with the starting location for the transfer in main memory, which correspond to segments within chains of contiguous physical memory. During a transfer, the address registers are updated to contain the location where the next portion of the incoming ethernet packet will be written in memory.