Microprocessor bus interface unit for interfacing an n-bit

Abstract

A bus interface unit disposed for incorporation within a microprocessor system having a local microprocessor bus, a memory unit, and a system bus coupled to the memory unit is disclosed herein. The bus interface unit includes a bus control unit having an address latch for latching N-bit memory addresses impressed upon the local microprocessor bus by the microprocessor. Each of the N-bit memory addresses identifies one or more M-bit memory locations within the memory unit. The bus interface unit further includes a multiplexing interface for transferring data associated with the M-bit memory locations between the system bus and the local microprocessor bus during microprocessor memory access cycles. A programmable wait state generator serves to control the duration of the microprocessor memory access cycles in order to accommodate address and data transfer between the system bus and the local microprocessor bus during both memory read and write access cycles. In a preferred implementation the N-bit memory addresses latched during microprocessor bus cycles correspond to a sequential pair of M-bit memory locations.