Semiconductor integrated device

Abstract

A semiconductor integrated device is disclosed which is capable of selectively executing a memory test and a logic test. The device includes a logic part for realizing a plurality of operation functions in logic, a memory part having a given integration and for storing data, a pad part including a pad for inputting/outputting a control signal according to respective tests, a switch part respectively connected to the logic part, the memory part, and the pad part, and a switch control part for controlling the switch part to thereby selectively control the memory test and the logic test. The semiconductor integrated device according to the present invention is capable of performing a separate logic test by dividing a memory fault and a logic fault on a memory testing path. The semiconductor integrated device has a memory signal path, a logic signal path, and a pad path which are selectively used. In this manner, the semiconductor integrated device enables division of a normal mode and a test mode, and also is capable of selectively testing a logic part and a memory part to thereby improve a quality of a chip embedding a memory. Furthermore, the semiconductor integrated device is capable of improving packaging efficiency without using a separate pin associated with memory control and data input/output.