The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 1998
Filed:
Mar. 27, 1996
Applicant:
Inventor:
Meisei Nishikawa, Tokyo, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kanagawa-ken, JP;
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371-21 ; 371 401 ;
Abstract
A memory circuit having a plurality of regions. A first rearranging circuit, controlled by a control circuit, rearranges plural bits of data having different significances when a first of the regions includes a defective portion and a first one of the plural bits is to be written into the first region, so that a second of the plural bits having lower significance than that of the first bit is written into another one of the plurality of regions. A second rearranging circuit, controlled by the control circuit, rearranges the plural bits of data read out from the memory circuit so that the first and second bits are returned to correct positions.