Verification of instruction and data fetch resources in a functional

Abstract

A system and method for verifying the correct behavior of instruction and data fetches and the order of instruction and data fetch resource modifications by a speculative and or out-of-order computer architecture under test is presented. An architectural model which models the high-level architectural requirements of the computer architecture under test, including instruction fetch resources and data fetch resources, executes test stimuli instructions in natural program order. A behavioral model, which models the high-level architectural requirements of the computer architecture, including instruction fetch resources and data fetch resources, executes the same test stimuli instructions, but according to the speculative and or out-of-order instruction execution behavior defined by the computer architecture under test. Modifications to instruction fetch resources and data fetch resources by the behavioral model are respectively recorded separately in a respective instruction fetch resource event queue and data fetch resource event queue. Upon detection of a fetch instruction event by the behavioral model, each instruction fetch resource event stored in the instruction fetch resource event queue which has a corresponding timestamp earlier than the timestamp of the detected fetch instruction event is applied to the architectural model in timestamp order. Separately, upon detection of a data access request event by the behavioral model, each data fetch resource event stored in the data fetch resource event queue which has a corresponding timestamp earlier than the timestamp of the detected data access event is applied to the architectural model in timestamp order.