Sound source chip having variable clock to optimize external memory

Abstract

In a sound source apparatus, a central processing unit is integrated in a semiconductor chip and operates in response to a primary operating clock signal for creating a control message. A tone generating unit is integrated in the same semiconductor chip and operates in response to a secondary operating clock signal for generating a musical tone according to the control message. A master clock generator generates a master clock signal having a desired frequency selected from a plurality of frequencies. A mode changer designates one of a first mode and a second mode corresponding to different operating speeds. A clock generator is provided for variably frequency-dividing the master clock signal to generate the primary operating clock signal and the secondary operating clock signal. The clock generator is responsive to the mode changer for changing a frequency ratio of the primary operating clock signal to the secondary operating clock signal between the first mode and the second mode. An external memory is provided separately from the semiconductor chip for storing information required for generation of the musical tone. A memory controller is provided for allotting a primary time slot to the central processing unit and a secondary time slot to the tone generating unit such as to optimize access to the external memory shared by the central processing unit and the tone generating unit. A cache memory is provided to speed up operation of the central processing unit.