The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 1998
Filed:
Feb. 26, 1996
International Business Machines Corp., Armonk, NY (US);
Abstract
A method and apparatus for verifying memory coherency of a simulated computer system. A verification logic unit is used for detecting the issuance of load and store instructions from the simulated system. Targets (registers or memory locations) representing the detected instructions are then stored in queues, and marked (colored) as not having been executed. After a detected instruction has been executed and completed, the corresponding target in the queue is marked as being completed. During every clock cycle of the apparatus, the verification logic unit monitors the queues for entries (Targets) marked as completed, which are then discarded.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile