The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 1998

Filed:

Mar. 28, 1995
Applicant:
Inventors:

Kenji Kashiwagi, Minamiashigara, JP;

Akira Yamagiwa, Kanagawa-ken, JP;

Masao Inoue, Sagamihara, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395821 ; 395306 ; 39575003 ; 395287 ; 326 30 ;
Abstract

A data bus circuit includes a plurality of data buses, a plurality of data processing units connected to each of the data buses for performing transmission and reception of data in response to a transmission control signal, at least a termination resistor connected to termination of the plurality of data buses, the termination resistor including a first resistance circuit for suppressing reflection of signals on the plurality of data buses upon transmission and reception of data of the plurality of data processing units and a second resistance circuit having a resistance value larger than that of the first resistance circuit, an output control circuit for producing the transmission control signal as to whether the plurality of data processing units perform transmission and reception of data or not, and a changing-over circuit for changing over to connect the first resistance circuit to the data buses through which transmission and reception of data is performed when at least one of the plurality of data processing units performs transmission and reception of data in response to the transmission control signal and to connect the second resistance circuit to the data buses through which transmission and reception of data is not performed when any of the plurality of data processing units does not perform transmission and reception of data, whereby a current flowing in the termination resistor can be reduced when data is not transmitted on the data bus and the low power consumption of the data bus circuit can be attained.


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