The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 1998
Filed:
Feb. 26, 1996
Applicant:
Inventor:
Yair Baydatch, Ramat Hasharon, IL;
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
36474504 ;
Abstract
An arithmetic logic unit includes overflow trap logic for an integer-multiply instruction. A multiply unit multiplies a pair of n-bit operands together and produces a n+1 bit result. The low order n-bits are returned as the multiplication result. A first overflow logic unit examines the leading bits of both operands and counts the number of leading bits which are equal to respective sign bits. If the count is smaller than n, an overflow trap is signalled. If not, then a second logic unit examines bits n and n-1 of the result and signals an overflow trap if these bits are not equal.