The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 1998
Filed:
Jun. 20, 1996
NEC Corporation, Tokyo, JP;
Abstract
A logic circuit design procedure comprises a step of deciding the feasibility of hardware after HDL description and functional verification, and a step of performing logic synthesis of the HDL description which has been determined to be feasible. The feasibility decision step comprises at least a decision on the possibility of spike transfer and a decision on oscillation. The spike transfer check step determines whether at least one of a clock signal and a reset signal of any sequential circuit is output from a combinational circuit. The oscillation check step determines whether an output signal of any combinational circuit is recursively input thereto without passing through a sequential circuit. Only the HDL description which passes the feasibility test is allowed to enter the logic synthesis stage.