The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 1998
Filed:
Aug. 01, 1996
Jonathan Lin, Milpitas, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Depletion mode pass gates utilized in a PLD to enable a gate voltage of Vcc to be applied for turn off, as opposed to a higher voltage required for enhancement type devices. With Vcc applied for turn off, gate oxide stress is reduced and chip reliability increased. A decoder utilizing PMOS transistors is further used to supply a negative gate voltage to enable turn off of the depletion mode pass gates. In one embodiment, to prevent pumping the power supply voltage above Vcc when supplying Vcc to gates of the pass gates, the decoder is an all PMOS device using PMOS transistors to connect Vcc to gates of the pass gates. In another embodiment both NMOS and PMOS transistors are utilized, with PMOS blocking transistors utilized to prevent a negative voltage from being applied to the NMOS transistors and causing current leakage. A negative voltage pump is further provided to supply a sufficient negative voltage.