Embedded memory for field programmable gate array

Abstract

A programmable logic device has a configuration memory which is partitioned so that it includes at least one subarray available through the programmable interconnect of the user configurable logic to be used as user memory. Subarrays of the configuration memory have independent access logic coupled with them, and coupled to the user logic array so that they may be used independently as user memories. Subarray memory access logic is provided for each subarray of memory elements, and connected to the logic cell array, and optionally to the plurality of input/output cells on the device, including a subarray decoder used for selecting addressed memory elements in the corresponding subarray in response to address signals and control signals supplied across the interconnect structures of the logic cell array, and a subarray I/O path used to provide input and output data signals between the interconnect structures of the logic cell array and addressed memory elements in the subarray. Thus, each subarray of memory elements, its corresponding subarray decoder and subarray I/O path, are independently configurable in the programmable logic device for use as user memory.