The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 1998
Filed:
Jun. 30, 1997
Yoshikazu Ohno, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A semiconductor device including a first wiring layer formed on a main surface of a semiconductor substrate, and a first insulating film layer having first and second contact holes which reach the main surface of the semiconductor substrate formed on the first wiring layer. A second wiring layer is formed on the first insulating film layer, and a first electric conductor, connected electrically to the semiconductor substrate, is formed in the first contact hole by self-alignment with respect to the first wiring layer and is isolated electrically from the first wiring layer. A second electric conductor, electrically connecting the second wiring layer to the semiconductor substrate is formed in the second contact hole by self-alignment with respect to the first wiring layer and is isolated electrically from the first wiring layer. A second insulating film layer is formed on the second wiring layer and has a third contact hole which reaches the first contact hole. A first electrode (or third wiring layer), formed on the second insulating film layer and in the third contact hole by self-alignment with respect to the second wiring layer, is electrically connected to the first electric conductor and is electrically insulated from the second wiring layer, since the bit line and gate electrode are not exposed in the contact hole when the contact hole was formed. Therefore, a semiconductor device of high integration is formed without any short circuit between the capacitor electrode and bit line or gate electrode and without any short circuit between the bit line and gate electrode.