The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 1998
Filed:
Mar. 20, 1997
Eric John Stacey, Pittsburgh, PA (US);
George Studley Bettencourt, Murrysville, PA (US);
Electric Power Research Institute, Inc., Palo Alto, CA (US);
Abstract
A high power inverter pole for a voltage sourced inverter suitable for providing compensation in electric power transmission and distribution systems, has a positive switching valve and a negative switching valve connected between closely spaced dc-source terminal, respectively, and a common ac terminal to form a current loop with minimum loop area thereby reducing stray loop inductance and limiting the overshoot voltage on serially connected electronic switches which make up the valves. In a preferred embodiment, the valves are mounted on opposite sides of the web of an insulative I-beam. The electronic switches are incorporated in modular switching units connected in series by C-channel connecting conductors having flanges bolted to the I-beam flanges. The modular units include broad, flat conductors bolted through end flanges to the C-channel connecting conductors. The electronic switches and anti-parallel diodes of the modular units are clamped between these broad, flat conductors. Cooling water is circulated through the broad, flat conductors which serve as heat sinks as well as providing low inductance electrical connections. In another embodiment of the invention, sections of the positive and negative switching valves are folded back on themselves to minimize loop area and hence again, reduce stray loop inductance.