One-hot overflow matrix with enhanced architecture and one-hot variable

Abstract

A one-hot overflow matrix which includes a first one-hot input comprised of a plurality n of parallel bits arranged in sequence from a zero bit position to an (n-1) bit position, a second one-hot input comprised of a plurality n of parallel bits arranged in sequence from a zero bit position to an (n-1) bit position, a plurality n of output gates (e.g., tri-state buffers) each having a first input, a second input, and an output, a data output line commonly coupled to the output of each of the output gates, a plurality n/2 of NOR gates each having one or more data inputs, and a data output, and a plurality (n/2-1) of OR gates each having one or more data inputs, and a data output. The data input(s) of each respective ith one of the NOR gates are respectively coupled to the zero bit position through ((n-1)-i) bit position bit(s) of the second one-hot input. The first input of each respective ith one of the output gates is coupled to the data output of a corresponding ith one of the NOR gates, and the second input of each respective ith one of the output gates is coupled to a corresponding ith bit position bit of the first one-hot input. The data input(s) of each respective jth one of the OR gates are respectively coupled to the (n-j) bit position through (n-1) bit position bits of the second one-hot input, where i=n/2 through (n-1), and j=(n/2-1) through 1.