The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 1998
Filed:
Dec. 12, 1996
Michael John Shay, Arlington, TX (US);
Mark Douglas Koether, Grand Prairie, TX (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An input/output buffer including a bidirectional node, an output stage, an input stage, and a control circuit. The output stage has a first n-channel transistor coupled between the bidirectional node and a voltage supply node for pulling-up the bidirectional node, and first and second p-channel transistors coupled between the bidirectional node and the voltage supply node for pulling-up the bidirectional node. The input stage has a first inverter stage coupled between the bidirectional node and a first intermediate node and a second inverter stage coupled between the bidirectional node and a second intermediate node. The input stage also has a second n-channel transistor coupled between the first intermediate node and a ground node and a third n-channel transistor coupled between the second intermediate node and the ground node. The control circuit is coupled to the output stage and to the input stage and enables the output stage when in an output mode and disables the output stage when in an input mode. The control circuit has a first mode which disables the first and second p-channel transistors and enables the first n-channel transistor for operation with a first voltage supply level present at the voltage supply node and which the enables the second inverter stage and which turns the third n-channel transistor off.