The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 1998

Filed:

Jun. 06, 1995
Applicant:
Inventors:

Akira Kuroyanagi, Okazaki, JP;

Masami Yamaoka, Anjo, JP;

Yoshifumi Okabe, Anjo, JP;

Yasuaki Tsuzuki, Anjo, JP;

Yutaka Tomatsu, Okazaki, JP;

Assignee:

Nippondenso Co. Ltd., Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257341 ; 257342 ; 257346 ;
Abstract

The present invention involves a vertical type semiconductor device whereby miniaturization and lowered ON resistance of a cell within the device can be achieved without impairing the functioning of the device. The line width of the gate electrode is made smaller to meeting the demand for miniaturization of the cell while the distance between the channel regions which are diffused into the portions below the gate during double diffusion remains virtually equal to that in the device of larger cell size having a low J.sub.FET resistance component. While the width of the gate electrode is set to be smaller, the mask members used during double diffusion are attached to the side walls of the gate electrode, where their width allows the source region to diffuse to the portion under the gate. Accordingly, miniaturization and lowered ON resistance of the cell can be achieved without impairing the functioning of the device.


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