Semiconductor memory device with improved read signal generation of data

Abstract

A semiconductor memory device with a pair of data lines for reading and writing data signals to and from a matrix of memory cells and an accelerator circuit for accelerating the generation of a data signal on at least one of the data lines is disclosed. Slow signal generation on the data lines is due to the characteristics of NFET pass gates passing high signals, or PFET pass gates passing low signals. In an implementation using NFET pass gates, the accelerator circuit includes a pair of cross-coupled PFET transistors, one of which is activated by the low signal on the opposing data line. The drains of the cross-coupled PFET transistors are coupled to the data lines, such that when the low signal on the opposing data line activates one of the PFETs, it supplies additional current to the data line receiving the high signal, so as to accelerate the generation of the high signal on the data line. Faster signal generation allows for the data line latches of the circuit to be set earlier, thus allowing the read cycle of the memory device to be faster. An additional result of the increased signal generation on the data line that is receiving a high signal is that at the end of the cycle when the two data lines are coupled together, their average voltage due to charge sharing tends to be closer to a desired midlevel voltage such that less power is required to bring the two data lines to the desired mid-level voltage at the end of the signal cycle.