The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 1998
Filed:
Jun. 16, 1997
Kamran Manteghi, Manteca, CA (US);
VLSI Technology, Inc., Sunnyvale, CA (US);
Abstract
A high density ball-grid array package for packaging an integrated-circuit die includes a laminated structure formed of a dielectric layer and a high conductive layer disposed thereon. The dielectric layer has a plurality of first drilled holes, and the conductive layer is formed with a desired pattern. An insulated layer is provided with a plurality of second drilled holes. The laminated substrate is bonded to the insulated substrate so that the plurality of first drilled holes are aligned with corresponding ones of the plurality of second drilled holes in order to form selective solderable areas on the bottom side of the package. The laminated structure has an open portion overlying a central region of the insulated substrate on the top side of the package. An integrated-circuit die is mounted in the central region of the insulated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the conductive layer of laminated structure. A plastic material is molded over the top surface of the die, bonding fingers and bonding wires. Finally, solder balls are attached to the selective solderable areas.