The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 1998

Filed:

Oct. 18, 1993
Applicant:
Inventors:

Mark W Hervin, Dallas, TX (US);

Ronald S McMahon, Plano, TX (US);

Assignee:

National Semiconductor, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395583 ; 395571 ; 395572 ; 39580023 ;
Abstract

A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing microinstructions. The method involves various steps. In one step, an instruction is received. In another step, a first microinstruction is issued from the memory. This first microinstruction comprises a control and a base address. In yet another step, a secondary address is determined, external from the memory, by evaluating a plurality of predetermined data. In a still another step, the base address and the secondary address are combined to form a destination address in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.


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