Method and apparatus for arbitrating access to main memory of a computer

Abstract

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus (e.g., peripheral devices). Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. Further, to reduce stalling of a processor seeking access to the main memory via the host bus and the internal bus, the host bus is able to gain access to the main memory using the internal bus during times in which the internal bus is temporarily not needed by the data transfer between the main memory and the peripheral devices. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with peripheral devices, and because the internal bus is occasionally freed up during the data transfer between the main memory and the peripheral devices.