On-chip primary cache testing circuit and test method

Abstract

A primary cache test system is supplied using a secondary cache that closely matches specifications of the primary cache. Coherency is maintained between the primary and secondary caches using inclusion by a write-once protocol. The test system includes software which suspends cache operations on receipt of an error signal from a secondary cache controller or by periodically pausing cache operations for cache operation monitoring. During suspension of cache operations, the software verifies the states of the primary cache against the states and data within the secondary cache. Signals on cache hit and hit-modified pins that are available on the microprocessor integrated circuit are monitored to detect various error conditions. Error analysis includes detection of invalid hits to the primary cache, incorrectly modified lines in the primary cache and misses to the primary cache that should be hits.