Micro rom testing system using micro rom timing circuitry for testing

Abstract

Micro ROM testing is provided using timing logic and clocks utilized in normal operation of the micro ROM. A PLA in the micro ROM has its output lines coupled to read amplifiers that receive values read from the PLA locations selected by address inputs. The read amplifiers latch the PLA values into timing generators to produce timing signals of various types supplied to a microcontroller associated with the micro ROM. A test signal is supplied to the timing generators to disconnect them from the outputs of the read amplifiers and to establish a scan chain composed of the timing generators connected in series. Non-overlapping clock signals supplied by a system clock of the microcontroller cause the latched PLA values to shift through the timing generators in the scan chain. At a scan output of the last timing generator in the scan chain, the PLA values are observed and compared with the values expected from the selected PLA locations.