Single transistor non-volatile electrically alterable semiconductor

Abstract

An electrically alterable semiconductor memory device having an array of memory cells formed by individual transistors. The structure of the memory cells is compact and facilitates high density memory devices and is particularly well suited for contactless, virtual ground arrays. The memory cells can be read and programmed a page at a time. The memory cells can also be programmed using source-side hot-electron injection with improved efficiency and lowered programming currents. In one embodiment, the structure of the memory cells include: a substrate having a diffused source region, a diffused drain region, and a channel region between the diffused source region and the diffused drain region; a select gate positioned adjacent to the channel region, the select gate being positioned over a first portion of the channel region, the first portion being adjacent to the diffused source region and extending therefrom towards the diffused drain region; a floating gate adjacent to the channel region, the floating gate being positioned over a second portion of the channel region, the second portion being adjacent to the diffused drain region and extending therefrom towards the diffused source region; and a control gate over the floating gate. By providing select gates in the memory cells, problematic reverse currents in adjacent unselected memory cells of a contactless, virtual ground array are blocked or prevented during programming. The invention also pertains to a method for fabricating the semiconductor memory device.