The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 1998

Filed:

Apr. 24, 1996
Applicant:
Inventor:

Barry E Burke, Lexington, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257219 ; 257221 ; 257224 ; 257248 ; 257249 ;
Abstract

A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode. The potential pocket is formed by an ion implantation into the semiconductor substrate, a region of an insulating layer having a thickness which differs from the thickness of the remainder of the insulating layer positioned between the gate electrode and the substrate, a second gate electrode positioned adjacent the first gate electrode, or a lightly or undoped second region of a resistive layer disposed adjacent the gate electrode.


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