Internal testability system for microprocessor-based integrated circuit

Abstract

A fault isolation system for use in an integrated circuit. The fault isolation system includes multiple input shift registers which are connected end-to-end, serial output to serial input, for convenient interface with a test data input and test data output that are controlled by the test access port controller (tap controller) of conventional JTAG circuitry that is frequently provided in such integrated circuits. The multiple input shift registers include parallel inputs which receive test data from test nodes within functional blocks such as general circuit blocks and linear bus alleys. The multiple input shift registers are efficiently controlled by a global controller which talks to many local controllers. The global controller distributes control signals that are received by the local controllers. The multiple input shift registers thereafter operate in accordance with the control signals and, in order to operate 'at speed,' also operate in time coordination with the local clock phases driving the functional block under observation. The multiple input shift registers preferably include polynomial feedback taps in order to generate a predictable 'signature' given a sequential set of parallel data subsequent to initiation to a known state.