Digital delay circuit and method

Abstract

A digital delay circuit structure includes a digital calibration circuit and a digital delayed signal generator. The digital delay circuit is automatically calibrated when a calibrate signal goes active. Once the auto-calibration process is completed, the circuit switches back to a normal delay mode operation where the digital delay circuit remains until the next transition of the calibrate signal. A calibration control circuit generates a sample gate signal which initiates a feedback signal to the input terminal delay chain circuit that causes the delay chain output signal to oscillate. A calibration counter circuit counts the oscillations and couples this information to a count decoder circuit which in turn generates a signal to select one of a plurality of taps in the delay chain circuit. The digital delay circuit automatically compensates for delay variations caused by process extremes, temperature, and average voltage changes.