The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 1998
Filed:
Dec. 21, 1995
Larry D Gross, Poughkeepsie, NY (US);
Richard W Cadovius, Cowansville, CA;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for manufacturing a cap for use in a semiconductor package is disclosed. The semiconductor package includes a semiconductor chip and a substrate. The chip is mounted with the substrate at a chip locus. The method preferably comprises the steps of placing a slug in a die, and exercising the die to cold flow the slug to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperating with the base to establish a well bounded by the walls and the base. The walls terminate in a plane, and the well clears the chip when the cap is mounted on the substrate at the chip locus. The invention further includes a cap for use in a semiconductor package. The cap comprises a structure cold flowed from a slug in a die to a predetermined cap configuration. The cap configuration includes a plurality of walls depending from a polygonal generally planar base and cooperates with the polygonal base to establish a well bounded by the plurality of walls and the polygonal base. The walls terminate generally in a termination plane, and the well clears the chip when the cap is abuttingly mounted at the termination plane on the substrate at the chip locus.