The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 1998
Filed:
Apr. 02, 1996
Ratan K Choudhury, Milpitas, CA (US);
Ashok K Kapoor, Palo Alto, CA (US);
Satish Menon, Milpitas, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A first metal layer is formed on a substrate of an integrated circuit and electrically interconnects a microelectronic device and an Input/Output (I/O) pad. A second metal layer is insulated from the first metal layer by a dielectric layer, and is connected directly only to the pad. A plurality of vias are formed through the dielectric layer, and electrically interconnect the first and second metal layers such that current can flow between the device and the pad through both metal layers and the vias. A higher scale of circuit integration is made possible by reducing the widths of the metal layers without reducing their combined current carrying capacity. An Electrostatic Discharge (ESD) protection device is connected to one or both of the first and second metal layers such that current can flow from the pad to the protection device during an ESD event through both metal layers and the vias. The increased current carrying capacity provided by the two metal layers and vias increases the resistance of the metal layers to damage induced by high current flow during ESD events.