The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 1998

Filed:

May. 12, 1997
Applicant:
Inventors:

Michele Palmieri, Settimo Milanese, IT;

Paola Galbiati, Monza, IT;

Lodovica Vecchi, Monza, IT;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438234 ; 438220 ; 438294 ; 438356 ; 438414 ;
Abstract

A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it. The process described allows the production of integrated devices with an additional buried layer while utilizing one fewer mask than conventional processes.


Find Patent Forward Citations

Palmieri, Michele. (1998). Process for the fabrication of semiconductor devices having various (U.S. Patent No. 5789288). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5789288

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