The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 1998

Filed:

Jul. 20, 1995
Applicant:
Inventors:

Tomohisa Kishigami, Obu, JP;

Katsuhisa Tsuji, Hoi-gun, JP;

Yoshiki Tatsutomi, Obu, JP;

Assignee:

Nippondenso Co., Ltd., Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ; H04L / ; H04L / ; H04L / ;
U.S. Cl.
CPC ...
375354 ; 375364 ; 375369 ; 370304 ; 370305 ; 370449 ;
Abstract

A data receiving unit includes a data receiving circuit for receiving, through a transmission path, transmission data which has been encoded into a predetermined transmission code by using a predetermined transmission clock signal and includes a reference pulse having a pulse width corresponding to a period of the transmission clock signal, a clock for generating a received clock signal in synchronization with the transmission data, and a data decoding circuit for decoding the transmission data received by the data receiving circuit using the received clock signal generated by the clock, where the clock includes an oscillator generating at least a reference clock having a period which is shorter than that of the transmission clock signal, a counter circuit counting an interval between points of change of the transmission data received by the data receiving circuit according to the reference clock signal, a reference pulse detector circuit for detecting the reference pulse on the basis of a count value from the counter circuit, and a received clock signal generating circuit for generating a received clock signal in synchronization with the transmission data by frequency-dividing the reference clock signal on the basis of the count value when the counter circuit counts the pulse width of the reference pulse.


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