Method for determining interconnection resistance of wire leads in

Abstract

A process determines a linear interconnection resistance R between two external access points of an electronic device. The device comprises a chip, a chip carrier and wiring between the chip and carrier. The chip comprises an ESD device such as a diode which is electrically connected between the two access points. To begin the process, various currents are injected from one of the access points to another and corresponding voltages are measured across the two access points. Alternately, various voltages are applied from one access point to the other and corresponding currents are measured. The applied voltages and injected currents all forward bias the ESD device. These current-voltage relationships are applied to an interconnection model algorithm to yield the interconnection resistance. The interconnection model algorithm is derived from an interconnection model equation using least squares as a maximum likelihood estimator applied to the interconnection model equation to deliver absolute roots of the interconnection model algorithm. The interconnection model equation models the circuit comprising the interconnection resistance and the ESD device except that the nonlinear parameters of the ESD device is untangled from the linear interconnection resistance.