The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 1998

Filed:

Sep. 10, 1997
Applicant:
Inventors:

Harutsugu Fukumoto, Anjo, JP;

Hiroaki Tanaka, Okazaki, JP;

Akiyoshi Asai, Aichi-gun, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257358 ; 257379 ; 257350 ; 257360 ; 257355 ;
Abstract

A SOI semiconductor integrate circuit device, which can protect against surges between a signal-input terminal and power-supply input terminal thereof to obtain an improved electrostatic withstand quantity, is disclosed. An inverter circuit which is an integrated circuit is formed in a thin-film semiconductor layer formed through an insulation film on a p-type silicon substrate. An n-type diode diffusion region, resistor diffusion region, and FET diffusion region are formed within the silicon substrate. An input portion of the inverter circuit is connected through the resistor diffusion region to a signal-input terminal IN. A power-supply input terminal VC is connected to a ground terminal GND through a reverse-biased diode D formed by the diode diffusion region. When surge is applied to the signal-input terminal IN, a parasitic diode DD composed by the resistor diffusion region and silicon substrate exhibits avalanche breakdown and surge voltage is bypassed. An electrostatic withstand quantity of the inverter circuit can be increased.


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