The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 1998

Filed:

Jun. 01, 1995
Applicant:
Inventors:

Hiroshi Haraguchi, Tokyo, JP;

Masahiro Abe, Yokohama, JP;

Wataru Nomura, Ichikawa, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438584 ; 438975 ; 148 332 ;
Abstract

Disclosed is an alignment mark for the X directional alignment of a chip area on a semiconductor wafer, for example. The alignment mark comprises recesses and projections formed on a semiconductor substrate. The recesses or projections are repeatedly arranged in the X direction. The X directional width of the recesses or projections is set smaller than the X directional width of a grain on a metal film formed on the recesses and projections or the average particle size, as viewed from above the semiconductor substrate. The projections may be formed by an insulating layer formed on the semiconductor substrate.


Find Patent Forward Citations

Haraguchi, Hiroshi. (1998). Method of making a semiconductor wafer with alignment marks (U.S. Patent No. 5786267). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5786267

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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