The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 1998
Filed:
Jul. 01, 1996
Manjunath Doreswamy, Sunnyvale, CA (US);
Aleksandar Pance, Sunnyvale, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
Disclosed is an automated method for adjusting wire lengths between connected circuit elements of an integrated circuit. The method includes the following steps: (1) receiving a value specifying a wire length that must be provided between terminals of two integrated circuit elements in the integrated circuit design; (2) defining a routing region in which the wire can be routed; and (3) automatically specifying a wire route including a serpentine section within the routing region for connecting the terminals. The serpentine section will include one or more legs sized to ensure that the wire route has the specified wire length. Specifically disclosed is the application of this method to size wiring between two clock buffers in separate and adjacent stages of a clock distribution network. The two clock buffers may be provided in third and fourth stages of the clock distribution network.