Distributed free register tracking for register renaming using an

Abstract

In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages to process instructions for the processor, the processor including a register translation system that controls a renaming of physical registers of the processor to logical registers thereof, a tracking circuit that tracks availability of the physical registers for the renaming, method of operation thereof and processor containing the same. The tracking circuit includes: (1) ID, AC and EX tracking registers corresponding to the ID, AC and EX processing stages, each of the ID, AC and EX tracking registers containing tracking indicators corresponding to physical registers of the processor to be tracked, (2) read detection circuitry that changes a particular tracking indicator of a particular tracking register from a 'not-read' state to a 'read' state when an instruction being processed in a particular processing stage corresponding to the particular tracking register causes the particular processing stage to read a value from a particular physical register corresponding to the particular tracking indicator and (3) combinatorial circuitry that designates the particular physical register as available for the renaming only when all particular tracking indicators of the ID, AC and EX tracking registers corresponding to the particular physical register are in the 'not-read' state.