Modular mirrored cache memory battery backup system

Abstract

A battery backup mirrored cache memory module for a cache dynamic random access memory (DRAM) system that senses the V.sup.cc level supplied through the cache controller to the cache memory and, if the cache controller supplied V.sup.cc falls below a preset threshold level, the battery backup apparatus switches the cache memory array to a backup battery V.sup.cc source, and a backup refresh control generator unit that is also powered by the backup battery V.sup.cc source. The cache DRAM, backup battery, and backup refresh generator are physically contained in a single module that can be disconnected from the cache controller and host computer system while preserving cache memory contents. The backup system is installed in an operating host system for recovery of the cache memory contents and/or resumption of execution of the program that was running when the V.sup.cc power failure occurred. Cache memory reliability is further enhanced by providing two cache memory banks that are accessed simultaneously using a common address and have a stored parity bit with each data entry. When a read access is made, a cache memory bank selector selects one of the bank's output data if no parity error is detected. If one bank has a parity error, the other bank's output can be used to correct the data in the bank with the parity error.