The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 1998
Filed:
Nov. 18, 1996
Gopal Gopinathan, Cary, NC (US);
William Wong, Milton, MA (US);
Furuno Diagnostics America, Inc., Cary, NC (US);
Abstract
A beamformer includes an array having a plurality of channels of delay elements which are constructed of charge coupled devices (CCDs). Each channel has a first plurality of delay elements cells which perform beam focussing and a second plurality of delay elements which perform beam steering. In this manner beam steering delays and beam focussing delays may be calculated independently. Typically, the second plurality of delay elements have a resolution which is typically coarser than the resolution of the first plurality of delay element cells which function to focus the beam. A signal may be inserted into any one of the delay elements of the first plurality to provide an appropriate delay. The signal is then output from the last delay element of the first plurality to the second plurality. The signal is delivered from a selected delay element of the second plurality to a charge sum data bus, which combines the signals output from each of the channels. This combined signal may then be output to a common offset delay block, which in turn outputs the array signal having a common delay. A plurality of such arrays may be coherently combined. If the required delay exceeds the maximum delay provided by each channel, the output of each array may be offset by a maximum delay of a preceding array in the plurality of arrays in order to coherently combine all of the arrays. Desirably, a shift register having a single enable bit is dynamically controlled to select the appropriate delay by selecting a CCD delay cell.