Parallel multiply accumulate array circuit

Abstract

A circuit performs controlled multiplication, shifting, and accumulation operations. A sequence of pairs of input operand signals and corresponding arithmetic control signals are synchronously supplied to the circuit by an external controller. Arithmetic control values include a downshift value (DV) for controlling shifting operations and an accumulate number (AN) for controlling accumulation operations. The circuit includes n booth multipliers (BMs) for receiving the sequenced information and a first multiplexer having n inputs each coupled to a BM output. Each BM has a BM memory control unit. For rounding purposes during downshifting, each P register of each BM is primed before each multiply operation. An internal control circuit monitors the status of each BM. If all of the BMs are 'busy' and another multiply request arrives, then a stall signal is sent to the external controller. When the status of BM.sub.i is 'finished,' the internal control circuit selects the output of BM.sub.i to output through the first MUX. A downshift circuit is controlled to shift the output of the first MUX according to the corresponding DV. A plurality of m accumulators each have an input coupled to receive a downshift circuit output. The AN signal is used to select which of the plurality of m accumulators to enable via an accumulate select bus. Each of the m accumulators may be implemented with an adder and a register. The external controller can select one of the m accumulators to receive the final product value.