Multiplier circuit for performing inverse quantization arithmetic

Abstract

An inverse quantizer includes a multiplier circuit using two adder/subtracter stages to perform a multiplication operation between the quantizer scale value and the weight value. The inverse quantizer may be employed within a video decoder circuit such an an MPEG decoder. The multiplier circuit includes a control unit which receives the seven bit quantizer scale value. The control unit is configured to control a set of multiplexers which select either the weight value and/or bit shifted versions of the weight value to be operated upon by the two stage adder. Accordingly, each multiplexer circuit includes certain bit-shifted versions of the weight value as inputs. The control unit controls the multiplexer circuits such that appropriate inputs are channeled through the multiplexer circuits for operation by a pair of adder/subtracter circuits. The control unit further controls each adder/subtracter circuit such that appropriate arithmatic operations are performed upon the input values in accordance with the particular quantizer scale value. A given quantizer scale value causes the control unit to control the multiplexer circuits as well as the adder/subtracter circuits in a manner such that the desired result is obtained. Since for any given quantizer scale value, no more than a total of three values representing versions of the weight must be arithmatically operated upon, only two adder/subtracter circuits are required to achieve the results of a multiplication between the weight value and the quantizer scale value.