Layout method for semiconductor memory device obtaining high bandwidth

Abstract

A semiconductor memory device architecture and method thereof obtains a high data bandwidth by forming multiple input/output lines. A unit array has a plurality of reference blocks formed in a length direction of the device, each reference block storing a plurality of memory cells. A sub array has a plurality of unit arrays formed in a longitudinal direction perpendicular to the length direction. A word line selects memory cells from within the reference blocks, the word line extending in the length direction. A pair of bit lines and a pair of data input/output lines extend in the longitudinal direction. The pair of data input/output lines are correspondingly connected to 2.sup.n (n=1,2, . . . ) pairs of bit lines. A read select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a read operation. A write select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a write operation. A column gate connects the pair of bit lines to the pair of data input/output lines. A column select line extends in the longitudinal direction and controls the column gate, and a pair of main data input/output lines are connected correspondingly through a multiplexer to a plurality of data input/output lines.