Programmable logic device with partially configurable memory cells and a

Abstract

A field programmable gate array having memory cells that can be partially reconfigured comprises an array of tiles having logic blocks and routing structures, an array of associated memory cells, a data register, an address register and a memory configuration device. The data register is coupled to store data in the memory cells, and the address register is coupled to address the memory cells by column. The memory configuration device preferably comprises a register, a decoder and a control unit for receiving a bit stream including a skip command or a write command plus data. The memory configuration device allows the memory cells to be partially reconfigured by allowing each column of memory cells to be selectively written or skipped in response to the command inserted into the bit stream. The present invention also comprises a method for partially reconfiguring the memory cells including the steps of: retrieving a packet from a bit stream; determining whether the packet is a write command; if the packet is a write command, retrieving a frame of data from the bit stream and loading the frame of data into a data register; if the packet is a write command, loading the frame of data into a group of memory cells; and incrementing an address register.