The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 1998

Filed:

Jul. 11, 1996
Applicant:
Inventors:

David Rees, Overton, GB;

Sandeep Pant, Basingstoke, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
326 86 ; 326 81 ; 326 83 ; 327319 ; 327328 ;
Abstract

An output buffer having a reduced-swing output includes a p-channel pullup transistor as the primary pullup device. A biasing circuit is provided so as to bias the gate terminal of the pullup p-channel transistor to a predetermined level. The predetermined level is effective to cause the p-channel pullup transistor to shut off when the output of the buffer reaches a reduced magnitude output level (V.sub.OH). In the disclosed embodiment, the biasing circuit includes an n-channel transistor connected between the gate and drain terminals of the p-channel pullup transistor. The biasing circuit also includes a p-channel transistor having a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the pullup transistor. When the output of the buffer is desired to be in a logic high state, both of the biasing transistors are 'ON.' The voltage applied to the gate of the pullup transistor is, in effect, the result of the voltage divider effect between the 'ON' resistances of the two biasing transistors. These transistors divide the voltage between V.sub.cc and the voltage on the drain of the pullup transistor. A third p-channel transistor is provided, and which has a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the p-channel pullup transistor. This transistor is provided to turn the pullup transistor completely 'OFF' in predetermined situations, such as when a pulldown circuit is to be activated, or when the buffer is to be tri-stated.


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