Gate overlap drain source flash structure

Abstract

The presently preferred embodiment of the invention provides a memory structure that eliminates the thick gate associated with the offset of the FAMOS transistor and reduces the standard 225 angstrom offset to a 100 angstrom offset required for FN tunnelling. The 100 angstrom offset is realized uniformly underneath the entire area of the floating poly. The invention uses transistors each having a 100 angstrom offset to realize both erase and programming functions. The present invention realizes an erasing feature through an erase transistor and an ERL line. However, the programming of the cell will be realized through the programming transistor. As a result, a double poly flash cell will function like an EEPROM. This functioning eliminates the hot electron tunnelling required to program conventional double poly flash cells and results in a significant reduction in chip real estate. The reduction allows the present invention to be scaled to next generation architectures. By eliminating the need for hot electron programming, a lower source voltage can be implemented. FN tunnelling can be realized with very low currents, typically in the area of 10 nano amps, which can be generated from the internal power supply on a typical chip. Implementation of the present invention with present technology eliminates one masking step during fabrication.