The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 1998
Filed:
Feb. 28, 1997
Dzung Joseph Tran, Hillsboro, OR (US);
Mark Warren Acuff, Hillsboro, OR (US);
TransLogic Technology, Inc., Beaverton, OR (US);
Abstract
A gate array architecture adapted for circuits containing transmission gates. In one embodiment, the gate array architecture contains a base row having at least four alternating P- and N-channel transistor rows. The transistor rows are positioned between a first voltage and a second voltage rail. In another embodiment, the rows adjacent the first and second voltage rails have larger transistors to facilitate connection of the transistors as inverters or buffers. The rows more remotely positioned from the first and second voltage rails have smaller transistor sizes to facilitate connection of the transistors as transmission gates. The gate array architecture is particularly efficient when used to create serial multiplexer-based circuits.