Self-aligned mosfet gate/source/drain salicide formation

Abstract

MOSFET device structure includes planarized trench isolation field oxide regions formed in a silicon substrate, a layer of gate oxide formed on the substrate to electrically insulate the polysilicon gate from the substrate, oxide sidewall spacers formed on sidewalls of the polysilicon gate and the gate oxide, and LDD N-regions formed in the substrate adjacent to the field oxide regions and beneath the sidewall spacers to define a channel region in the substrate beneath the polysilicon gate. A layer of polysilicon is deposited on the above-defined structure and a chemical mechanical polishing step is performed to form raised source/drain polysilicon regions that are self-aligned to the LDD N- regions. N-type dopant is then implanted into the polysilicon gate and into the raised source/drain polysilicon regions. A first rapid thermal processing (RTP) step is then performed to activate the N-type dopant and to diffuse N-type dopant from the raised source/drain polysilicon regions into the underlying LDD N- regions to form N+ junctions within the LDD N- regions. A layer of cobalt is then deposited on the polysilicon gate and on the raised source/drain polysilicon regions in ultra high vacuum. The cobalt layer is then implanted with heavy ions to mix the cobalt and silicon at the cobalt/poly interface. A thin titanium nitride film is then formed on the cobalt layer to protect the cobalt film from nitrogen diffusion during RTP. A second RTP step is then performed to form cobalt salicide on the raised source/drain polysilicon regions and on the polysilicon gate.