The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 1998
Filed:
Apr. 11, 1997
Erik S Jeng, Taipei, TW;
Tzu-Shih Yen, Taipei, TW;
Vanguard International Semiconductor Corporation, Hsin-Chu, TW;
Abstract
A method for manufacturing crown-shaped stacked capacitors on dynamic random access memory using a single photoresist mask to make the node contacts and capacitor bottom electrodes was achieved. After forming the FET gate electrodes from a first polysilicon layer and the bit lines from a second polysilicon layer, a thick planar BPSG and a hard mask composed of polysilicon or silicon nitride is deposited. Openings are etched in the hard mask and partially into the BPSG. Sidewall spacers, composed of Si.sub.3 N.sub.4 or TEOS oxide, are formed in the openings and a special selective high density plasma etch and the etchant gas mixture of O.sub.2, CHF.sub.3, CF.sub.4, CO, C.sub.4 F.sub.8, and Ar is used to form the node contact openings in the BPSG to the FETs. A conformal third polysilicon layer is then deposited and a second masking material is used to define the bottom electrodes having a crown-shape in the BPSG openings. After removing the hard mask, the second masking material, and the BPSG between electrodes, an interelectrode dielectric layer is formed on the bottom electrodes. An N.sup.+ doped fourth polysilicon layer is deposited to form the top electrodes and to complete the crown-shaped stacked capacitors.